sa7121a: 128 bit read - only manchester coded transponder http://www.sames.co.za preliminary features eeprom flexibility of data configuration 128 bits of otp data factory programmed and locked customer specific configuration of stored data data output in manchester mode carrier frequency 100 to 300 khz on - chip resonance capacitor no ext ernal charge storage capacitor required on - chip full wave rectifier on - chip data modulator on - chip high voltage protection / regulation on - chip rf frequency clock extractor / prescaler low power dissipation description this device is manufactured in the sames 1.2m n - well eeprom process. it has 128 bits, factory pre - programmed and locked in eeprom memory. read data is manchester coded. the device has an on - chip rectification circuit that converts the incoming rf signal to dc power feeding v dd . th ere is also an on - chip data modulator, which works in conjunction with the rectifier. the time base is extracted by an on - chip rf clock extractor. high voltage protection across the coil inputs is provided internally. the energy is stored on capacitance on chip due to low internal power consumption. the device has an on - chip resonance capacitor connected between the coil1 and coil2 pads. these features result in a single external component count, comprised of, only the coil. data is read at the rf interfac e by means of the on - chip modulator. the stored bits are clocked out sequentially during the read operation. an internal power - on reset is provided which allows the device to start reading out data at low voltages for improved tag range. applications acc ess control industrial automation asset tracking spec ? 1124 (rev. 1) 2 3 - 05 - 03 1/10
http://www.sames.co.za preliminary sa7121a pad connections pad description pad no. name description 1 coil1 external coil connection 2 coil2 external coil connection 3 v dd supply voltage 4 test test pad 5 test tes t pad 6 test test pad 7 v ss ground 8 test test pad 3 6 7 vss vdd test test test test 8 5 4 2 1 coil2 coil1 2/10
http://www.sames.co.za preliminary sa7121a block diagram test test test clock reset power-on vdd test vss eeprom control logic clock extractor resonance capacitor cr coil1 coil2 vss vdd prescaler rectifier full wave modulator high voltage protection 3/10
http://www.sames.co.za preliminary sa7121a absolute maximum ratings parameter symbol min max unit note supply voltage v dd - 0.3 9.4 v 1,2,3,4,5 esd protection c= 100pf r = 1.5kohm , human body model . mil - std - 883c method 3015 vpesd - tbd v 3,8 peak voltage across coil1 or coil2 to v ss v coil1,2 - v ss - 10 +10 v 3,6 peak current through coil 1,2 i coil1,2 - 30 +30 ma 3,7 storage temperature tst - 55 +125 o c 3 note 1: duration no t to exceed 10 seconds, and no logic switching. note 2: referenced to vss note 3: stresses above those listed under ? absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating conditions section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect the device reliability. note 4: vdd level when a bsolute maximum current goes through coil inputs. note 5: vdd level when absolute maximum voltage is across coil inputs. note 6: maximum peak voltage at coil1 or coil2 of incoming rf signal with v ss as reference. clamping by front - end protection circuitry. note 7: maximum allowed peak current of incoming rf signal. note 8: tbd - to be determined. handling procedures although the device has built - in esd protection, adherence to anti - static procedures for cmos devices is required. electrical characteristics dc operating conditions parameter symbol min typ max unit condition dynamic current i dd 3 6 a v dd = 3v static current i dds 1 a v dd = 3v, clock stopped, coil1 & coil2 shorted to v ss voltage when power - on reset comes out of reset v por 1.2 1.6 2 v during power - up v dd ? v ss rising histereses on power - on rest v porh 200 - 600 mv between coming out of reset and going back into reset data retention t dr 10 - - years programmed supply voltage v dd 2 - 5.5 1) v at specified current at coil1 or coil2, operating temperature top - 40 +70 o c note: 1) maximum voltage is defined when forcing 10 ma on the coil inputs. 4/10
http://www.sames.co.za preliminary sa7121a ac operating conditions clocking parameter symbol min typ max unit condition rf carrier frequency at coil1,2 f rf 50 125 300 khz sustained rf from base station number of rf carrier cycles per bit n b 32 64 - coil inputs parameter symbol min typ max unit condition negative excursion of coil1 or coil2 v cn - 0.6 - 0.65 - 0.7 v peak level referenced to vss modulated voltage drop v cm tbd 3.3 tbd v unmodulated coil1 or coil2 voltage referenced to v ss = 5.5v modulated voltage drop v cm tbd 3.0 tbd v unmodulated coil1 or coil2 voltage referenced to v ss = 5.0v modulated voltage drop v cm tbd 0.875 tbd v unmodulated coil1 or coil2 vo ltage referenced to v ss = 2.5 v resonance capacitor c r 1) 170 1) pf measured between coil1 and coil2 note: 1) for a single batch the tolerance is 3%. from batch to batch the tolerance is 30%. tbd - to be determined. 5/10
http://www.sames.co.za preliminary sa7121a functional descrip tion the circuit is built up out of several functional blocks, control logic, coil interface, the power - on reset, and the memory module (eeprom). the chip activates automatically during power - up as a result of the built in power - on reset. coil interface power is derived from a full wave rectifier bridge. data modulation takes place by loading the coil inputs to the bridge with a modulating circuit. the coil interface includes on - chip high voltage protection. the system clock for the chip is derived by mea ns of a clock extractor coupled to the rectifier circuit. the clock extractor / prescaler is the time base generator for data reading. data is read from the eeprom to the coil interface where the rf signal is modulated by the data in the manchester coded m ode. memory array data storage: the data eeprom is arranged in an 16x8 bit array composed of 16 columns of 8 bit bytes. the 128 bits of data stored in the array can be configured in any way as agreed with the client, and is factory programmed and locked in that way. this gives otp (one time programmable) security. memory map the flexibility of programming allows custom memory mapping. control logic the control logic gets its clock from the clock extractor / prescaler and facilitates the reading of the data stored in the data eeprom. timing specifications the coil1 and coil2 pads modulate the incoming rf signal with manchester encoded data. the data will repeatedly be read out serially until the power is reduced sufficiently to activate the power on r eset again. there are 64 rf carrier cycles for each data bit. this is the nominal setting. an optional setting of 32 rf cycles per bit can be selected during wafer manufacture. data output data output takes place according to manchester encodin g. 6/10 n = 64 rf clock cycles per data bit data rf clock dn+1 cln-1 cln-2 cln-3 cl8 cl7 cl6 cl5 cl4 cl3 cl2 cl1 cl0 dn-1 dn no data no data manchester 0 data5 1 1 1 0 data7 data6 1 0 0 data4 data3 data2 data1 data 0 no data no data data5 data7 data6 data4 data3 data2 data1 data 0 0 1 1 1 0 1 0 0 data
http://www.sames.co.za preliminary sa7121a typical application the chip powers up via the coil1 and coil2 pads, deriving its energy from the rf carrier wave through the resonating tank circuit made up by the external inductor, l r , and internal capacitor, c r . an optional additional extern al capacitor can be added for special requirements. the data will automatically start modulating the rf signal as soon as the chip has powered up to the power - on reset level. the built in voltage protection and regulation insures protection against high vo ltage from the tank circuit. the value of l r is determined by the following relationship. f r = 1 / ( 2 p ? l r * c r ) where f r is the resonance frequency. for a typical internal c r of 170 pf and for f r at 125 khz, l r = 9.54 mh r r l c coil1 coil2 3 6 7 vss vdd test test test test 8 5 4 2 1 7/10
http://www.sames.co.za preliminary sa7121a package and ordering information pcb form 2.66 mm 1.50 mm 8.0 mm 4.0mm 1.00 mm max 1.00 mm capacitor height** *note that an optional smd capacitor is not required normally due to internal capacitor on chip. the device is supplied without an smd capacitor. **note that the height of some smd capacitors c ould exceed the height of the glob. 0.5 mm board thickness 0.2 mm max opti onal smd capacitor* 8/10
http://www.sames.co.za preliminary sa7121a chip form ordering information data rate at 32 clocks per bit in chip form sa7121 32 ic in pcb form sa7121 32 cob data rate at 64 clocks per bit in chip form sa7121 64 ic in pcb form sa7121 64 cob 144 1820 1610 100 100 coil1 coil2 dimensions are in micrometers ic thickness is 280 micrometers 25 micrometers the outer dimensions of the ic is g iven as the distance from saw channel centre to saw channel centre and will be smaller than indicated due to material removed during sawing 144 112 v dd v ss 1524.5 1564 1322 1322 857 144 144 151.5 144 9/10
http://www.sames.co.za preliminary sa7121a disclaimer: the information contained in this document is confidential and proprietary to south african micro - electronic systems (pty) l td ("sames") and may not be copied or disclosed to a third party, in whole or in part, without the express written consent of sames. the information contained herein is current as of the date of publication; however, delivery of this document shall not und er any circumstances create any implication that the information contained herein is correct as of any time subsequent to such date. sames does not undertake to inform any recipient of this document of any changes in the information contained herein, and s ames expressly reserves the right to make changes in such information, without notification, even if such changes would render information contained herein inaccurate or incomplete. sames makes no representation or warranty that any circuit designed by ref erence to the information contained herein, will function without errors and as intended by the designer. any sales or technical questions may be posted to our e - mail address below: id_security@sames.co.za for the latest updates on datas heets, please visit our web site: http://www.sames.co.za south african micro - electronic systems (pty) ltd tel: 012 333 - 6021 tel: int +27 12 333 - 6021 fax: 012 333 - 8071 fax: int +27 12 333 - 8071 p o box 15888, lynn east 0039, republic of south africa 33 eland street, koedoespoort industrial area, pretoria republic of south africa 10/10
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